Electronic circuits, such as integrated microcircuits, are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microcircuit devices typically involves many steps, sometimes referred to as the “design flow.” The particular steps of a design flow often are dependent upon the type of microcircuit, its complexity, the design team, and the microcircuit fabricator or foundry that will manufacture the microcircuit. Typically, software and hardware “tools” verify the design at various stages of the design flow by running software simulators and/or hardware emulators. These steps aid in the discovery of errors in the design, and allow the designers and engineers to correct or otherwise improve the design. These various microcircuits are often referred to as integrated circuits (IC's).
Several steps are common to most design flows. Initially, the specification for a new circuit is transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the circuit. With this logical design, the circuit is described in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). The logic of the circuit is then analyzed, to confirm that it will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as “functional verification.”
After the accuracy of the logical design is confirmed, it is converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific electronic devices (such as transistors, resistors, and capacitors) that will be used in the circuit, along with their interconnections. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams. The relationships between the electronic devices are then analyzed, often mathematically, to confirm that the circuit described by the device design will correctly perform the desired functions. This analysis is sometimes referred to as “formal verification.” Additionally, timing verifications are often made at this stage, by for example simulating the various clocks employed to drive the device.
Once the components and their interconnections are established, the design is again transformed, this time into a physical design that describes specific geometric elements. This type of design often is referred to as a “layout” design. The geometric elements, which typically are polygons, define the shapes that will be created in various layers of material to manufacture the circuit. Typically, a designer will select groups of geometric elements representing circuit device components (e.g., contacts, channels, gates, etc.) and place them in a design area. These groups of geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Lines are then routed between the geometric elements, which will form the wiring used to interconnect the electronic devices. Layout tools (often referred to as “place and route” tools) are commonly used for both of these tasks.
As indicated, device verification often takes place prior to the actual manufacturing of the device. As a result, hardware description languages are typically employed to model the hardware and act as an embodiment for testing purposes. Additionally, hardware verification languages are often used to provide a stimulus with which to test the hardware design. More particularly, a hardware verification languages may be employed to generate a sequences (or typically many sequences) of inputs to be applied to the hardware designs. To facilitate generation of test sequences, hardware verification languages usually have a number of test sequence generation routines, such as, for example, a constrained random generation routine.
In order to facilitate reuse of hardware components between designs and to assist in the verification of proprietary hardware components, such as, for example, a proprietary integrated circuit, vendors and manufactures will typically provide a verification component for selected portion of a design or for selected reusable hardware components. A verification component allows for the seamless integration of the selected hardware component into the verification environment.
As those of skill in the art can appreciate, legacy hardware verification languages, such as, for example, the e verification language, were typically proprietary in nature. Accordingly, verification components compatible with these proprietary hardware verification languages are not compatible with the modern open verification methodologies (“OVM”) in use today. As a result, reusing legacy verification components in modern OVM based verification is difficult.